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零件编号
产品描述 (功能)
ADF4360-9 查看數據表(PDF) - Analog Devices
零件编号
产品描述 (功能)
比赛名单
ADF4360-9
Clock Generator PLL with Integrated VCO
Analog Devices
ADF4360-9 Datasheet PDF : 24 Pages
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Data Sheet
ADF4360-9
TIMING CHARACTERISTICS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
1
Refer to the Power-Up section for the recommended power-up procedure for this device.
CLK
t
4
t
5
DATA
DB23 (MSB)
t
2
t
3
DB22
DB2
DB1
(CONTROL BIT C2)
LE
t
1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t
7
t
6
Rev. B | Page 5 of 24
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