ADP3212AMNR2G 查看數據表（PDF） - ON Semiconductor

零件编号

产品描述 (功能)

比赛名单

ADP3212AMNR2G

7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller

ON Semiconductor 

ADP3212A, NCP3218A

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

VVID = VDAC = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

Parameter

Symbol

Conditions

Min

Typ

Max Units

VOLTAGE CONTROL − VOLTAGE ERROR AMPLIFIER (VEAMP)

FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC

−200

+200 mV

FB, LLINE Offset Voltage (Note 2)

VOSVEA

Relative to CSREF = VDAC

−0.5

+0.5

mV

LLINE Bias Current

ILLINE

−100

+100

nA

FB Bias Current

IFB

−1.0

+1.0

mA

LLINE Positioning Accuracy

VFB − VVID

Measured on FB relative to VVID, LLINE

−77.5

−80

−82.5

mV

forced 80 mV below CSREF

COMP Voltage Range (Note 2)

COMP Current

VCOMP

ICOMP

COMP = 2.0 V, CSREF = VDAC

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

0.85

4.0

V

mA

−0.75

6.0

COMP Slew Rate

SRCOMP

CCOMP = 10 pF, CSREF = VDAC,

Open loop configuration

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

V/ms

15

−20

Gain Bandwidth (Note 2)

VID DAC VOLTAGE REFERENCE

GBW

Non−inverting unit gain configuration,

RFB = 1 kW

20

MHz

VDAC Voltage Range (Note 2)

See VID table

0

1.5

V

VDAC Accuracy

VFB − VVID

Measured on FB (includes offset),

relative to VVID

VVID = 0.5000 V to 1.5000 V,

T = −10°C to 100°C

−7.5

VVID = 0.5000 V to 1.5000 V,

T = −40°C to 100°C

−9.0

VVID = 0.3000 V to 0.4875 V,

T = −10°C to 100°C

−9.0

VVID = 0.3000 V to 0.4875 V,

T = −40°C to 100°C

−10

mV

+7.5

+9.0

+9.0

+10

VDAC Differential Non−linearity

(Note 2)

−1.0

+1.0 LSB

VDAC Line Regulation

VDAC Boot Voltage

Soft−Start Delay (Note 2)

ΔVFB

VBOOTFB

tDSS

VCC = 4.75 V to 5.25 V

Measured during boot delay period

Measured from EN pos edge to

FB = 50 mV

0.001

%

1.100

V

200

ms

Soft−Start Time

tSS

Measured from FB = 50 mV to FB settles

1.4

ms

to 1.1 V within 5%

Boot Delay

tBOOT

Measured from FB settling to 1.1 V within

60

ms

5% to CLKEN neg edge

VDAC Slew Rate (Note 2)

Soft−Start

Non−LSB VID step, DPRSLP = H, Slow

C4 Entry/Exit

Non−LSB VID step, DPRSLP = L, Fast

C4 Exit

LSB VID step, DVID transition

GPU Mode, Non−LSB VID step, Fast

Entry/Exit

0.0625

0.25

1.0

0.4

1.0

LSB/

ms

FBRTN Current

IFBRTN

VOLTAGE MONITORING and PROTECTION − POWER GOOD

−90 −200 mA

CSREF Undervoltage Threshold

CSREF Overvoltage Threshold

VUVCSREF

VOVCSREF

Relative to nominal VDAC voltage

Relative to nominal VDAC voltage,

T = −10°C to 100°C

T = −40°C to 100°C

−240 −300 −360 mV

mV

150

200

250

140

200

250

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

http://onsemi.com

5

Share Link: