AK8858 查看數據表（PDF） - Asahi Kasei Microdevices

零件编号

产品描述 (功能)

比赛名单

AK8858

PS/SD Multi Format Video Decoder

Asahi Kasei Microdevices 

[7] Functional description

[7.1] Analog circuit description

Analog circuit block is shown below.

XTI XTO

[AK8858]

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

Clock

Module

CLAMP AAF

PGA1

MUX

CLAMP AAF

CLAMP AAF

MUX PGA2

VREF

10-bit

ADC1

10-bit

ADC2

PLL Feed-back

Information

10bit

10bit

VRP VCOM VRN IREF

When decode YPbPr component video signal, Pb/Pr signal is converted to digital data by PGA2 and ADC2

after the data was sampled at sample hold circuit.

Time sharing operational status of ADC and PGA is shown below (PGA2 and ADC2 is shown as VPGA2,

VADC2, VPGA3 and VADC3).

XTI XTO

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

Clock

Module

CLAMP AAF

PGA1

MUX CLAMP AAF

VPGA2

CLAMP AAF

VPGA3

VREF

10-bit

ADC1

10-bit

VADC2

10-bit

VADC3

PLL Feed-back

Information

10bit

10bit

10bit

VRP VCOM VRN IREF

MS1230-E-00

- 21 -

2010/9

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