AK8858 查看數據表（PDF） - Asahi Kasei Microdevices
零件编号
产品描述 (功能)
比赛名单
AK8858 Datasheet PDF : 96 Pages
| |||
[AK8858]
[7.1.1] CVBS signal decoding
The data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
[7.1.2] S(Y/C) video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
C signal data is converted to digital at PGA2 and ADC2. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
[7.1.3] 525i/625i YPbPr component video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
Pb signal data is converted to digital at VPGA2 and VADC2. Sampling clock is 27MHz.
Pr signal data is converted to digital at VPGA3 and VADC3. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
AAF Chracteristic (except Progressive)
[7.1.4] 525p/625p YPbPr component video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 54MHz.
Pb signal data is converted to digital at VPGA2 and VADC2. Sampling clock is 27MHz.
Pr signal data is converted to digital at VPGA3 and VADC3. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼12MHz), −30dB (54MHz)
MS1230-E-00
AAF Chracteristic (Progressive)
- 22 -
2010/9
Share Link: 