AK8858 查看數據表（PDF） - Asahi Kasei Microdevices

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产品描述 (功能)

比赛名单

AK8858

PS/SD Multi Format Video Decoder

Asahi Kasei Microdevices 

The relation between CLPSTAT and BCLPSTAT is shown as follows.

Clamp Timing Pulse

[AK8858]

CLPSTAT[1:0] = 00

CLPSTAT[1:0] = 01

CLPSTAT[1:0] = 11

CLPSTAT[1:0] = 10

CLPWIDTH[1:0]

1/128H delay

1/128H advance

2/128H advance

Sync tip / middle clamp

CLPSTAT[1:0] = 00

BCLPSTAT[2:0] = 000

CLPSTAT[1:0] =10

BCLPSTAT[2:0] = 000

CLPSTAT[1:0] =10

BCLPSTAT[2:0] = 111

CLPSTAT[1:0] =00

BCLPSTAT[2:0] = 110

CLPWIDTH[1:0]

2/128H advance

3/128H advance

2/128H advance

Back porch clamp

Clamp current value setting

CLPG[1:0]: Set the current value of fine clamp in analog block.

Setting

Clamp current value

Notes

00

Min.

01

Middle 1 (Default)

10

Middle 2

11

Max.

Middle 1 = (Min. x 3 times)

Middle 2 = (Min. x 5 times)

Max. = (Min. x 7 times)

UDG[1:0]: Set the current value of rough clamp in analog block.

Setting

Clamp current value

Notes

00

Min. (Default)

01

Middle 1

10

Middle 2

11

Max.

Middle 1 = (Min. x 2 times)

Middle 2 = (Min. x 3 times)

Max. = (Min. x 4 times)

Its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp).

MS1230-E-00

- 26 -

2010/9

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