AS6C3216-55TIN 查看數據表（PDF） - Alliance Semiconductor

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AS6C3216-55TIN

32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

Alliance Semiconductor 

Rev. 1.0

AS6C3216

32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL

TEST CONDITION

VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V

Data Retention Current

VCC = 1.2V

-SL

IDR

CE# ≧VCC-0.2V or CE2≦0.2V

other pins at 0.2V or VCC-0.2V

-SLI

Chip Disable to Data

Retention Time

tCDR

See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

MIN.

1.2

-

-

TYP.

-

8

8

MAX.

3.6

80

120

UNIT

V

µA

µA

0

-

tRC*

-

-

ns

-

ns

Vcc

CE#

Vcc(min.)

tCDR

VIH

VDR ¡Ù 1.2V

CE# ¡Ù Vcc-0.2V

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Vcc

CE2

Vcc(min.)

tCDR

VIL

VDR ¡Ù 1.2V

CE2 ¡Ø 0.2V

Low Vcc Data Retention Waveform (3) (LB#, UB# controlled)

Vcc

LB#,UB#

Vcc(min.)

tCDR

VIH

VDR ¡Ù 1.2V

LB#,UB# ¡Ù Vcc-0.2V

Vcc(min.)

tR

VIL

Vcc(min.)

tR

VIH

Alliance Memory, Inc.

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