AS6C3216-55TIN 查看數據表（PDF） - Alliance Semiconductor

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AS6C3216-55TIN

32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

Alliance Semiconductor 

Rev. 1.0

AS6C3216

32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

Address

Dout

tRC

tAA

Previous Data Valid

tOH

Data Valid

READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)

Address

CE#

CE2

tRC

tAA

tACE

LB#,UB#

OE#

Dout

tBA

tOE

tOLZ

tBLZ

tCLZ

High-Z

tOH

tOHZ

tBHZ

tCHZ

Data Valid

High-Z

Notes :

1.WE#is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low.

3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting

parameter.

4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.

Alliance Memory, Inc.

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