CA3310(2001) 查看數據表（PDF） - Intersil

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CA3310
(Rev.:2001)

CMOS, 10-Bit, A/D Converters with Internal Track and Hold

Intersil 

CA3310, CA3310A

Device Operation

The CA3310 is a CMOS 10-bit, analog-to-digital converter

that uses capacitor-charge balancing to successively

approximate the analog input. A binarily weighted capacitor

network forms the D-to-A “Heart” of the device. See the

Functional Diagram of the CA3310.

The capacitor network has a common node which is connected

to a comparator. The second terminal of each capacitor is

individually switchable to the input, VREF+ or VREF-.

During the first three clock periods of a conversion cycle, the

switchable end of every capacitor is connected to the input.

The comparator is being auto-balanced at its trip point, thus

setting the voltage at the capacitor common node.

During the fourth period, all capacitors are disconnected

from the input, the one representing the MSB (D9) is

connected to the VREF + terminal, and the remaining

capacitors to VREF-. The capacitor-common node, after the

charges balance out, will represent whether the input was

above or below 1/2 of (VREF+ - VREF).

At the end of the fourth period, the comparator output is stored

and the MSB capacitor is either left connected to VREF+ (if the

comparator was high) or returned to VREF-. This allows the

next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF-).

At the end of periods 5 through 12, capacitors representing

the next to MSB (D8) through the next to LSB (D1) are

tested, the result stored, and each capacitor either left at

VREF+ or at VREF -.

At the end of the 13th period, when the LSB (D0) capacitor is

tested, D0 and all the previous results are shifted to the

output registers and drivers. The capacitors are reconnected

to the input, the comparator returns to the balance state, and

the data-ready output goes active. The conversion cycle is

now complete.

Clock

The CA3310 can operate either from its internal clock or

from one externally supplied. The CLK pin functions either

as the clock output or input. All converter functions are

synchronous with the rising edge of the clock signal.

Figure 16 shows the configuration of the internal clock. The

clock output drive is low power: if used as an output, it

should not have more than 1 CMOS gate load applied, and

wiring capacitance should be kept to a minimum.

OPTIONAL

EXTERNAL

CLOCK

CLK

INTERNAL

ENABLE

INTERNAL

CLOCK

OPTIONAL

CLOCK

ADJUST

100K

REXT

50K

FIGURE 16. CLOCK CIRCUITRY

18pF

The REXT pin allows adjusting of the internal clock

frequency by connecting a resistor between REXT and CLK.

Figure 6 shows the typical relationship between the resistor

and clock speed, while Figure 7 shows clock speed versus

temperature and supply voltage.

The internal clock will shut down if the A/D is not restarted after

a conversion. This is described under Control Timing. The clock

could also be shut down with an open collector driver applied to

the CLK pin. This should only be done during the sample

portion (the first three periods) of a conversion cycle, and might

be useful for using the device as a digital sample and hold: this

is described further under Applications.

If an external clock is supplied to the CLK pin, it must have

sufficient drive to overcome the internal clock source. The

external clock can be shut off, but again only during the sample

portion of a conversion cycle. At other times, it must be above

the minimum frequency shown in the specifications.

If the internal or external clock was shut off during the

conversion time (clock cycles 4 through 13) of the A/D, the

output might be invalid due to balancing capacitor droop.

An external clock must also meet the minimum tLOW and

tHIGH times shown in the specifications. A violation may

cause an internal miscount and invalidate the results.

Control Signals

The CA3310 may be synchronized from an external source

by using the STRT (Start Conversion) input to initiate

conversions, or if STRT is tied low, may be allowed to free-

run. In the free-running mode, illustrated in Figure 1, each

conversion takes 13 clock periods.

The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes

place. After the start of the next period 1 (specified by TD

data), the output is updated.

The DRDY (Data Ready) status output goes high (specified

by tD1 DRDY) after the start of clock period 1, and returns

low (specified by tD2 DRDY) after the start of clock period 2.

DRDY may also be asynchronously reset by a low on DRST

(to be discussed later).

If the output data is to be latched externally by the DRDY

signal, the trailing edge of DRDY should be used: there is no

guaranteed set-up time to the leading edge.

The 10 output data bits are available in parallel on three- state

bus driver outputs. When low, the OEM input enables the most

significant byte (D2 through D9) while the OEL input enables

the two least significant bits (D0, D1). tEN and tDIS specify the

output enable and disable times, respectively. See Figure 2.

When the STRT input is used to initiate conversions,

operation is slightly different depending on whether an

internal or external clock is used.

Figure 3 illustrates operation with an internal clock. If the

STRT signal is removed (at least tR STRT) before clock

10

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