CA3310, CA3310A
Timing Diagrams
CLK
tD1 DRDY
DRDY
D0 - D9
INPUT
1
2
3
4
5 - 12
13
tD2 DRDY
tHIGH
tD DATA
DATA N - 1
TRACK N
HOLD
1
2
3
tLOW
DATA N
TRACK N + 1
tD APR
FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH
OEL OR OEM
D0 - D1 OR
D2- D9
OFF TO HIGH
OFF TO LOW
tEN
50%
50%
tDIS
90%
ZL = 50pF TO GND
1kΩ TO GND
TO OUTPUT PIN
10%
ZL = 50pF TO GND
1kΩ TO VDD
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
13
1
CLK
(INTERNAL)
tR STRT
STRT
DRDY
INPUT
HOLD
2
TRACK
3
4
5
tD CLK
tW STRT
DON’T CARE
tD3 DRDY
HOLD
FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK
6