CA3310(2001) 查看數據表（PDF） - Intersil
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产品描述 (功能)
比赛名单
CA3310 Datasheet PDF : 16 Pages
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CA3310, CA3310A
Absolute Maximum Ratings
Digital Supply Voltage VDD . . . . . . . . . . . . . . VSS -0.5V to VSS +7V
Analog Supply Voltage (VAA+) . . . . . . . . . . . . . . . . . . . . VDD ±0.5V
Any Other Terminal . . . . . . . . . . . . . . . . VSS -0.5V to VDD + 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Drain Current, per Output . . . . . . . . . . . . . . . . . . ±35mA
Total DC Supply or Ground Current. . . . . . . . . . . . . . . . . . . . ±70mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum
Maximum
Storage Temperature (TSTG)
Lead Temperature (Soldering
....
10s)
.
.
.
.
.
.
.
.
.
.
-65oC
......
to
.
150oC
300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications TA = 25×oC, VDD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz, Unless
Otherwise Specified
PARAMETER
TEST CONDITIONS
ACCURACY (See Text For Definitions)
Resolution
Differential Linearity Error
CA3310
CA3310A
Integral Linearity Error
CA3310
CA3310A
Gain Error
CA3310
CA3310A
Offset Error
CA3310
CA3310A
ANALOG INPUT
Input Resistance
In Series with Input Sample Capacitors
Input Capacitance
During Sample State
Input Capacitance
During Hold State
Input Current
Static Input Current
Input + Full-Scale Range
At VIN = VREF+ = 5V
At VIN = VREF - = 0V
STRT = V+, CLK = V+
At VIN = VREF+ = 5V
At VIN = VREF - = 0V
(Note 3)
Input - Full-Scale Range
(Note 3)
Input Bandwidth
From Input RC Time Constant
DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Over VDD = 3V to 6V (Note 3)
Over VDD = 3V to 6V (Note 3)
Except CLK
Input Capacitance
(Note 3)
Input Current
CLK Only (Note 3)
DIGITAL OUTPUTS D0 - D9, DRDY
High-Level Output Voltage
Low-Level Output Voltage
Three-State Leakage
ISOURCE = -4mA
ISINK = 6mA
Except DRDY
Output Capacitance
Except DRDY (Note 3)
MIN
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF - +1
VSS -0.3
-
70
-
-
-
-
4.6
-
-
-
TYP
-
±0.5
±0.25
±0.5
±0.25
±0.25
-
±0.25
-
330
300
20
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-
-
-
MAX
UNITS
-
Bits
±0.75
LSB
±0.5
LSB
±0.75
LSB
±0.5
LSB
±0.5
LSB
±0.25
LSB
±0.5
LSB
±0.25
LSB
-
-
-
+300
-100
1
-1
VDD +0.3
VREF + -1
-
Ω
pF
pF
µA
µA
µA
µA
V
V
MHz
-
30
±1
10
±400
% of VDD
% of VDD
µA
pF
µA
-
V
0.4
V
±1
µA
20
pF
4
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