CDB6403 查看數據表（PDF） - Cirrus Logic

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CDB6403

Echo-Cancelling Codec

Cirrus Logic 

CS6403

Register SSI_CR2

B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

PDC PDSD MGD res

res

res

res

res AV3 AV2 AV1 AV0

0

0

0

0

0

0

0

0

0

0

0

0

This register is cleared at Reset by the SSI. This register is read/written by the CPU every sample time.

BIT

PDC

PDSD

MGD

res

AV3-AV0

NAME

Power Down Codec

Power Down Speaker

Driver

Microphone 26 dB Gain

Disable

Reserved for test

ADC Volume

"R" indicates value after Reset

VALUE

0R

1

0R

1

0R

1

00000 R

0000 R

.

.

1111

FUNCTION

Normal operation.

The entire codec is powered down.

Normal operation.

Only the speaker driver in the codec is powered

down.

Normal operation.

The 26 dB microphone preamp is bypassed.

Must be 00000.

ADC volume control is implemented in the CPU, with

the attenuation being -3 dB times the ADC-volume

value.

22

DS192PP6

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