CY7C1328G(2012) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1328G Datasheet PDF : 22 Pages
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CY7C1328G
Pin Definitions
Pin
TQFP
Type
Description
A0, A1, A
37, 36, 32, 33,
34, 35, 44, 45,
46, 47, 48, 49,
50, 80, 81, 82,
99, 100
Input-
synchronous
Address inputs used to select one of the 256 K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
sampled active. A[1:0] are fed to the two-bit counter.
BWA, BWB
93,94
Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
synchronous SRAM. Sampled on the rising edge of CLK.
GW
88
Input- Global write enable input, active LOW. When asserted LOW on the rising edge of CLK,
synchronous a global write is conducted (all bytes are written, regardless of the values on BW[A:B] and
BWE).
BWE
87
Input- Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
synchronous must be asserted LOW to conduct a byte write.
CLK
89
Input- Clock input. Used to capture all synchronous inputs to the device. Also used to increment
clock the burst counter when ADV is asserted LOW, during a burst operation.
CE1
98
Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
97
Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
92
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
86
Input- Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
83
Input- Advance input signal, sampled on the rising edge of CLK, active LOW. When
synchronous asserted, it automatically increments the address in a burst cycle.
ADSP
ADSC
84
Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW.
synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
85
Input- Address strobe from controller, sampled on the rising edge of CLK, active LOW.
synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
64
Input- ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
asynchronous non-time-critical “sleep” condition with data integrity preserved. During normal operation,
this pin has to be low or left floating. ZZ pin has an internal pull-down.
DQs,
DQP[A:B]
58, 59, 62, 63,
68, 69, 72, 73,
74, 8, 9, 12,
13, 18, 19, 22,
23, 24
I/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate
condition.
VDD
VSS
VDDQ
15, 41, 65, 91 Power supply Power supply inputs to the core of the device.
17, 40, 67, 90 Ground Ground for the core of the device.
4, 11, 20, 27, I/O power Power supply for the I/O circuitry.
54, 61, 70, 77 supply
VSSQ
5, 10, 21, 26, I/O ground Ground for the I/O circuitry.
55, 60, 71, 76
Document Number: 38-05523 Rev. *J
Page 5 of 22
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