CY7C1328G(2012) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1328G Datasheet PDF : 22 Pages
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CY7C1328G
Truth Table
The Truth Table for part CY7C1328G is as follows. [1, 2, 3, 4, 5]
Operation
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
ZZ mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None
H X XL X
LX
X X L–H Tristate
None
L L XL L
XX
X X L–H Tristate
None
L X HL L
XX
X X L–H Tristate
None
L L XL H
LX
X X L–H Tristate
None
L X HL H
LX
X X L–H Tristate
None
X X XH X
XX
X X X Tristate
External
L H LL L
XX
X L L–H Q
External
L H LL L
XX
X H L–H Tristate
External
L H LL H
LX
L X L–H D
External
L H LL H
LX
H L L–H Q
External
L H LL H
LX
H H L–H Tristate
Next
X X XL H
HL
H L L–H Q
Next
X X XL H
HL
H H L–H Tristate
Next
H X XL X
HL
H L L–H Q
Next
H X XL X
HL
H H L–H Tristate
Next
X X XL H
H
L
L X L–H D
Next
H X XL X
H
L
L X L–H D
Current
X X XL H
HH
H
L L–H Q
Current
X X XL H
HH
H H L–H Tristate
Current
H X XL X
HH
H
L L–H Q
Current
H X XL X
HH
H H L–H Tristate
Current
X X XL H
HH
L X L–H D
Current
H X XL X
HH
L X L–H D
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2.
WRITE =
GW = H.
L
when
any
one
or
more
byte
write
enable
signals
(BWA,
BWB)
and
BWE
=
L
or
GW
=
L.
WRITE
=
H
when
all
byte
write
enable
signals
(BWA,
BWB),
BWE,
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4.
The SRAM always initiates a read cycle when
the ADSP or with the assertion of ADSC. As a
ADSP
result,
is asserted, regardless of
OE must be driven HIGH
the state of
prior to the
GW,
start
oBfWthEe,worritBeWcyXc.lWe troiteasllomwaythoecocuutrpountslytoontrissutabtsee.qOuEenist
clocks after
a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05523 Rev. *J
Page 8 of 22
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