CY7C1328G(2012) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1328G Datasheet PDF : 22 Pages
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CY7C1328G
safety precaution, DQX are automatically tri-stated whenever a
write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1328G provides a two-bit wraparound counter, fed by
A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
01
00
11
10
11
00
11
10
01
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
00
01
Second
Address
A1:A0
01
10
Third
Address
A1:A0
10
11
10
11
00
11
00
01
Fourth
Address
A1:A0
11
10
01
00
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Test Conditions
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ > VDD 0.2 V
ZZ > VDD 0.2 V
ZZ < 0.2 V
ZZ active to snooze current
This parameter is sampled
ZZ inactive to exit snooze current This parameter is sampled
Min
–
–
2tCYC
–
0
Max
40
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Document Number: 38-05523 Rev. *J
Page 7 of 22
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