CY7C1329H-133AXC(2011) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1329H-133AXC Datasheet PDF : 20 Pages
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CY7C1329H
Truth Table [2, 3, 4, 5, 6, 7]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
Address Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
Address Used
None
None
None
None
None
None
External
External
External
External
External
Next
CE1 CE2 CE3
H
X
X
L
L
X
L
X
H
L
L
X
L
X
H
X
X
X
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
X
X
X
ZZ ADSP ADSC ADV WRITE OE
L
X
L
X
X
X
L
L
X
X
X
X
L
L
X
X
X
X
L
H
L
X
X
X
L
H
L
X
X
X
H
X
X
X
X
X
L
L
X
X
X
L
L
L
X
X
X
H
L
H
L
X
L
X
L
H
L
X
H
L
L
H
L
X
H
H
L
H
H
L
H
L
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
X
X
X
L
H
H
X
X
L
X
H
X
X
L
X
X
X
X
L
H
H
X
X
L
X
X
X
X
L
H
X
X
X
L
H
H
X
X
L
X
H
X
X
L
X
X
X
X
L
H
H
L
H
H
H
L
H
L
H
L
H
H
H
L
L
X
H
L
L
X
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
X
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3.
WRITE = L when any one
BWB, BWC, BWD), BWE,
or more Byte
GW = H.
Write
Enable
signals
(BWA,
BWB,
BWC,
BWD)
and
BWE
=
L
or
GW
=
L.
WRITE
=
H
when
all
Byte
Write
Enable
signals
(BWA,
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6.
The SRAM always initiates a read cycle when
the ADSP or with the assertion of ADSC. As a
ADSP
result,
is asserted, regardless of
OE must be driven HIGH
the state of
prior to the
GW,
start
oBfWthEe,WorriBteWc[yAc:Dle].
Writes may
to allow the
occur only on subsequent
outputs to Tri-State. OE is
clocks
a don't
after
care
for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05673 Rev. *E
Page 7 of 20
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