CY7C1340G 查看數據表（PDF） - Cypress Semiconductor

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CY7C1340G

4-Mbit (128K x 32) Pipelined DCD Sync SRAM

Cypress Semiconductor 

Functional Block Diagram

A0,A1,A

MODE

ADV

CLK

ADSC

ADSP

BWD

BWC

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

ADDRESS

REGISTER

2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR Q0

DQD

BYTE

WRITE REGISTER

DQc

BYTE

WRITE REGISTER

DQB

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

ENABLE

REGISTER

PIPELINED

ENABLE

CY7C1340G

DQD

BYTE

WRITE DRIVER

DQC

BYTE

WRITE DRIVER

DQB

BYTE

WRITE DRIVER

DQA

BYTE

WRITE DRIVER

MEMORY

ARRAY

OUTPUT

OUTPUT

SENSE

AMPS

REGISTERS

BUFFERS

DQs

E

INPUT

REGISTERS

SLEEP

ZZ

CONTROL

Document #: 38-05522 Rev. *D

Page 2 of 16

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