CY7C1340G 查看數據表（PDF） - Cypress Semiconductor

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CY7C1340G

4-Mbit (128K x 32) Pipelined DCD Sync SRAM

Cypress Semiconductor 

Partial Truth Table for Read/Write[2, 7]

Function

GW

Read

H

Read

H

Write byte A - DQA

H

Write byte B - DQB

H

Write byte C - DQC

H

Write byte D - DQD

H

Write all bytes

H

Write all bytes

L

CY7C1340G

BWE

H

L

L

L

L

L

L

X

BWA

X

H

L

H

H

H

L

X

BWB

X

H

H

L

H

H

L

X

BWC

X

H

H

H

L

H

L

X

BWD

X

H

H

H

H

L

L

X

Note:

7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05522 Rev. *D

Page 7 of 16

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