HI5780-EV 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

比赛名单

HI5780-EV

10-Bit, 80 MSPS, High Speed, Low Power D/A Converter

Intersil 

Timing Diagrams (Continued)

tPW1

HI5780

tPW2

CLK

D9-D0

tSU

tSU

tSU

tHLD

tHLD

tHLD

50%

tPD

tSETT

1/2 LSB

CHANGE

IOUT

tSETT

tPD

tPD

tSETT

1/2 LSB

CHANGE

FIGURE 3. PROPAGATION DELAY, SETUP TIME AND MINIMUM PULSE WIDTH DIAGRAM

Pin Descriptions

PIN

1-7, 30-32

9

13, 28

15, 27

20, 21

23

25

11

24

23

18

17

19

14

22

PIN NAME

DESCRIPTION

D0 (LSB) thru Digital Data Bit 0, the least significant bit thru digital data Bit 9, the most significant bit.

D9 (MSB)

CLK

Data Clock Pin 100kHz to 80MHz.

DVDD

DGND

Digital Logic Supply +5V.

Digital Ground.

AVDD

BLK

AGND

Analog Supply +5V.

Output Blanking pin. When set (‘1’) this pin zeros the IOUT pin.

Analog Ground Supply Current Return pin.

PD

Power Down Mode pin. This pin when set (‘1’) places the HI5780 in lower power mode and zeros the

output. Power consumption is reduced.

IOUT

IOUT

REFOUT

IREF

VREF

VB

Current Output pin.

Complementary Current Output pin.

Bandgap Reference Voltage Output.

Reference Current setting resistor connected from here to Ground.

Reference Voltage Input pin.

Bias Voltage Generator Bypass Capacitor connected from here to Ground.

VG

Reference Amplifier Bypass Capacitor connected from here to AVDD.

10-1720

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