IDT71V124S15 查看數據表（PDF） - Integrated Device Technology
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IDT71V124S15
Integrated Device Technology
IDT71V124S15 Datasheet PDF : 8 Pages
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IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Ranges)
71V124S15
71V124S20
Symbol
Parameter
Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
ns
tAA
Address Access Time
____
15
____
20
ns
tACS
Chip Select Access Time
____
15
____
20
ns
tCLZ(1)
Chip Select to Output in Low-Z
tCHZ(1)
Chip Deselect to Output in High-Z
E tOE
Output Enable to Output Valid
N C tOLZ(1)
Output Enable to Output in Low-Z
tOHZ(1)
Output Disable to Output in High-Z
I N A tOH
Output Hold from Address Change
T E S S tPU(1)
Chip Select to Power-Up Time
R C 24 N tPD(1)
Chip Deselect to Power-Down Time
A S 1 G WRITE CYCLE
I tWC
Write Cycle Time
P E V S tAW
Address Valid to End of Write
L 1 E tCW
Chip Select to End of Write
7 D tAS
Address Set-up Time
O R tWP
Write Pulse Width
S E W tWR
Write Recovery Time
D E tDW
Data Valid to End of Write
B R N tDH
Data Hold Time
O O R tOW(1)
Output Active from End of Write
FO tWHZ(1)
Write Enable to Output in High-Z
3
____
3
____
0
7
0
8
____
7
____
8
0
____
0
____
0
5
0
7
4
____
4
____
0
____
0
____
____
15
____
20
15
____
12
____
12
____
0
____
12
____
0
____
8
____
0
____
3
____
0
5
20
____
15
____
15
____
0
____
15
____
0
____
9
____
0
____
4
____
0
8
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3484 tbl 08
6.4 2
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