IDT82V2052E 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

比赛名单

IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

Type

RD1/RDP1 O

RD2/RDP2

Pin No.

34

26

Description

RDn: Receive Data output for Channel 1~2

In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI or HDB3 line code rules.

CV1/RDN1

CV2/RDN2

33 CVn: Code Violation indication

27 In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a full

clock cycle. HDB3 line code violation can be indicated if the HDB3 decoder is enabled. When AMI decoder is selected, bipolar

violation will be indicated.

In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single rail

mode is chosen.

RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2

In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data

if CDR is bypassed.

RCLK1

O

RCLK2

Active edge and level select:

Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also select-

able. Refer to 3.3.8 RECEIVE PATH SYSTEM INTERFACE for details.

35 RCLKn: Receive Clock output for Channel 1~2

25 This pin outputs a 2.048 MHz receive clock. Under LOS conditions with AIS enabled (bit AISE=1), RCLKn is derived from

MCLK.

In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn in

single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn.

MCLK

I

LOS1

O

LOS2

REF

I

If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This signal

can be used in applications with external clock recovery circuitry.

30 MCLK: Master Clock input

A built-in clock system that accepts a 2.048 MHz reference clock. This reference clock is used to generate several internal

reference signals:

• Timing reference for the integrated clock recovery unit.

• Timing reference for the integrated digital jitter attenuator.

• Timing reference for microcontroller interface.

• Generation of RCLKn signal during a loss of signal condition.

• Reference clock to transmit All Ones, all zeros and PRBS pattern. Note that for ATAO and AIS, MCLK is always used

as the reference clock.

• Reference clock during Transmit All Ones (TAO) condition or sending PRBS in hardware control mode.

The loss of MCLK will turn TTIP/TRING into high impedance status.

32 LOSn: Loss of Signal Output for Channel 1~2

28 These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received

signal in channel n. The LOS pin will become low automatically when valid received signal is detected again. The criteria of

loss of signal are described in 3.5 LOS AND AIS DETECTION.

71 REF: reference resister

An external resistor (3kΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.

PIN DESCRIPTION

10

December 12, 2005

Share Link: