IDT82V2052E 查看數據表（PDF） - Integrated Device Technology
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IDT82V2052E Datasheet PDF : 70 Pages
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.8 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 30
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 30
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 30
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 31
3.9 LINE DRIVER FAILURE MONITORING ........................................................................... 31
3.10 MCLK AND TCLK ............................................................................................................. 32
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 32
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 32
3.11 MICROCONTROLLER INTERFACES ............................................................................. 33
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 33
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 33
3.12 INTERRUPT HANDLING .................................................................................................. 34
3.13 5V TOLERANT I/O PINS .................................................................................................. 35
3.14 RESET OPERATION ........................................................................................................ 35
3.15 POWER SUPPLY ............................................................................................................. 35
4 PROGRAMMING INFORMATION .............................................................................................. 36
4.1 REGISTER LIST AND MAP ............................................................................................. 36
4.2 Reserved Registers .......................................................................................................... 36
4.3 REGISTER DESCRIPTION .............................................................................................. 38
4.3.1 GLOBAL REGISTERS............................................................................................ 38
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 39
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 39
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 40
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 42
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 43
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.3.8 LINE STATUS REGISTERS ................................................................................... 47
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 48
4.3.10 COUNTER REGISTERS ........................................................................................ 49
5 HARDWARE CONTROL PIN SUMMARY .................................................................................. 50
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53
6.2 JTAG DATA REGISTER ................................................................................................... 53
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53
6.2.2 BYPASS REGISTER (BR)...................................................................................... 53
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 53
7 TEST SPECIFICATIONS ............................................................................................................ 56
8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 65
8.1 SERIAL INTERFACE TIMING .......................................................................................... 65
8.2 PARALLEL INTERFACE TIMING ..................................................................................... 66
Table of Contents
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December 12, 2005
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