IDT82V2052E 查看數據表（PDF） - Integrated Device Technology

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IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

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Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75 Ohm ................................................................... 19

Transmit Waveform Value For E1 120 Ohm ................................................................. 19

Impedance Matching for Transmitter ............................................................................ 20

Impedance Matching for Receiver ................................................................................ 21

Criteria of Starting Speed Adjustment........................................................................... 24

LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 25

LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26

AIS Condition ................................................................................................................ 26

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 27

EXZ Definition ............................................................................................................... 30

Interrupt Event............................................................................................................... 34

Global Register List and Map........................................................................................ 36

Per Channel Register List and Map .............................................................................. 37

ID: Device Revision Register ........................................................................................ 38

RST: Reset Register ..................................................................................................... 38

GCF: Global Configuration Register ............................................................................. 38

INTCH: Interrupt Channel Indication Register............................................................... 38

TERM: Transmit and Receive Termination Configuration Register .............................. 39

JACF: Jitter Attenuation Configuration Register ........................................................... 39

TCF0: Transmitter Configuration Register 0 ................................................................. 40

TCF1: Transmitter Configuration Register 1 ................................................................. 40

TCF2: Transmitter Configuration Register 2 ................................................................. 41

TCF3: Transmitter Configuration Register 3 ................................................................. 41

TCF4: Transmitter Configuration Register 4 ................................................................. 41

RCF0: Receiver Configuration Register 0..................................................................... 42

RCF1: Receiver Configuration Register 1..................................................................... 42

RCF2: Receiver Configuration Register 2..................................................................... 43

MAINT0: Maintenance Function Control Register 0...................................................... 43

MAINT1: Maintenance Function Control Register 1...................................................... 44

MAINT6: Maintenance Function Control Register 6...................................................... 44

INTM0: Interrupt Mask Register 0 ................................................................................. 45

INTM1: Interrupt Masked Register 1 ............................................................................. 45

INTES: Interrupt Trigger Edge Select Register ............................................................. 46

STAT0: Line Status Register 0 (real time status monitor)............................................. 47

STAT1: Line Status Register 1 (real time status monitor)............................................. 48

INTS0: Interrupt Status Register 0 ................................................................................ 48

INTS1: Interrupt Status Register 1 ................................................................................ 49

CNT0: Error Counter L-byte Register 0......................................................................... 49

CNT1: Error Counter H-byte Register 1 ........................................................................ 49

Hardware Control Pin Summary ................................................................................... 50

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December 12, 2005

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