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IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

3.2.4 TRANSMIT PATH LINE INTERFACE

The transmit line interface consists of TTIPn and TRINGn pins. The

impedance matching can be realized by the internal impedance matching

circuit or the external impedance matching circuit. If T_TERM[2] is set to

‘0’, the internal impedance matching circuit will be selected. In this case,

the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω or 120 Ω

internal impedance of TTIPn/TRINGn. If T_TERM[2] is set to ‘1’, the internal

impedance matching circuit will be disabled. In this case, the external

impedance matching circuit will be used to realize the impedance matching.

Figure-6 shows the appropriate external components to connect with

the cable for one channel. Table-4 is the list of the recommended imped-

ance matching for transmitter.

In hardware control mode, TERMn pin can be used to select impedance

matching for both receiver and transmitter on a per channel basis. If TERMn

pin is low, internal impedance network will be used. If TERMn pin is high,

external impedance network will be used. When internal impedance net-

work is used, PULSn pins should be set to select the specific internal imped-

ance in the corresponding channel. Refer to 5 HARDWARE CONTROL PIN

SUMMARY for details.

The TTIPn/TRINGn can also be turned into high impedance globally by

pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)

to ‘1’. In this state, the internal transmit circuits are still active.

In hardware control mode, TTIPn/TRINGn pins can be turned into high

impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-

TROL PIN SUMMARY for details.

Besides, in the following cases, TTIPn/TRINGn will also become high

impedance:

• Loss of MCLK;

• Loss of TCLKn (exceptions: Remote Loopback; Transmit internal

pattern by MCLK);

• Transmit path power down;

• After software reset; pin reset and power on.

Table-4 Impedance Matching for Transmitter

Cable

Configuration

Internal Termination

T_TERM[2:0]

PULS[3:0]

E1 / 75 Ω

E1 / 120 Ω

000

0000

001

0001

Note: The precision of the resistors should be better than ± 1%

3.2.5 TRANSMIT PATH POWER DOWN

The transmit path can be powered down individually by setting the

T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are

turned into high impedance.

In hardware control mode, the transmit path can be powered down by

setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-

WARE CONTROL PIN SUMMARY for details.

External Termination

RT

T_TERM[2:0]

PULS[3:0]

RT

0Ω

1XX

0001

9.4 Ω

0001

3.3 RECEIVE PATH

The receive path consists of Receive Internal Termination, Monitor

Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive

Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Atten-

uator, Decoder and LOS/AIS Detector. Refer to Figure-5.

3.3.1 RECEIVE INTERNAL TERMINATION

The impedance matching can be realized by the internal impedance

matching circuit or the external impedance matching circuit. If R_TERM[2]

is set to ‘0’, the internal impedance matching circuit will be selected. In this

case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω or

120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2] is set to ‘1’, the

internal impedance matching circuit will be disabled. In this case, the exter-

nal impedance matching circuit will be used to realize the impedance

matching.

Figure-6 shows the appropriate external components to connect with

the cable for one channel. Table-5 is the list of the recommended imped-

ance matching for receiver.

FUNCTIONAL DESCRIPTION

20

December 12, 2005

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