IR3084 查看數據表（PDF） - International Rectifier
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IR3084 Datasheet PDF : 45 Pages
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IR3084
PIN DESCRIPTIONS
PIN#
1
2−9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN SYMBOL
VIDSEL
VID7−0
VOSNS−
ROSC
VDAC
OCSET
VSETPT
IIN
VDRP
FB
EAOUT
RMPOUT
VBIAS
VCC
LGND
REGFB
REGDRV
REGSET
SS/DEL
VRRDY
ENABLE
DESCRIPTION
Selects the DAC table and the type of Soft Start. There are 4 possible modes of
operation: (1) GND selects VR10 DAC and VR11 type startup, (2) FLOAT (1.25V)
selects VR11 DAC and VR11 type startup, (3) VBIAS (6.9V) selects VR11 DAC and
legacy VR10 type startup, (4) VCC (12V) selects VR10 DAC and legacy VR10 type
startup. Additional details are provided in the Theory of Operation section.
Inputs to the D to A Converter. Must be connected to an external pull-up resistor.
Remote Sense Input. Connect to ground at the Load.
Connect a resistor to VOSNS− to program oscillator frequency and OCSET,
VSETPT, REGSET, and VDAC bias currents
Regulated voltage programmed by the VID inputs. Connect an external RC network
to VOSNS− to program Dynamic VID slew rate and provide compensation for the
internal Buffer Amplifier.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting a resistor from this pin to VDAC to program the threshold higher than the
possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not
float this pin as improper operation will occur).
Error Amp non-inverting input. Converter output voltage can be decreased from the
VDAC (VID) voltage with an external resistor connected to VDAC and an internal
current sink. Current sensing and PWM operation are referenced to this pin.
Current Sense input from the Phase ICs. Prior to startup, SS/DEL<0.6V, this pin is
pulled low by a 12.5K resistor to disable current balancing in the Phase ICs. When
SS/DEL>0.6V and EAOUT>0.35V, this pin is released and current balancing is
enabled. If current feedback from the Phase ICs is not required for implementing
droop or over-current protection connect this pin to LGND. To ensure proper
operation do not float this pin.
Buffered IIN signal. Connect an external RC network to FB to program converter
output impedance
Inverting input to the Error Amplifier.
Output of the Error Amplifier. When Low, provides UVL function to the Phase ICs.
Oscillator Output voltage. Used by Phase ICs to program Phase Delay
6.9V/6mA Regulated output used as a system reference voltage for internal circuitry
and the Phase ICs.
Power Input for internal circuitry
Local Ground for internal circuitry and IC substrate connection
Inverting input of the Bias Regulator Error Amp. Connect to the out put of the Phase
IC Gate Driver Bias Regulator.
Output of the Bias Regulator Error Amp.
Non-inverting input of the Bias Regulator Error Amp. Output Voltage of the Phase IC
Gate Driver Bias Regulator is set by an internal current source flowing into an
external resistor connected between this pin and ground.
Controls Converter Start-up and Over-Current Timing. Connect an external capacitor
to LGND to program.
Open Collector output that drives low during Start-Up and any external fault
condition. Connect external pull-up.
Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin
has a 100K pull-down resistor to GND.
Page 6 of 45
07/20/2005
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