IR3084 查看數據表（PDF） - International Rectifier
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IR3084 Datasheet PDF : 45 Pages
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IR3084
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 3. Feed−forward voltage mode control
with trailing edge modulation is used. A high−gain wide−bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to
program the slope of the PWM ramp and to provide the feed−forward control at each phase. The PWM ramp
slope will change with the input voltage and automatically compensate for changes in the input voltage. The input
voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to
changes in load current.
CONTROL IC
50%
DUTY
CYCLE
RAMP GENERATOR
VPEAK
VVALLEY
+
VBIAS
REGULATOR
-
VDAC
200 OHM
ERROR
AMP
IOFFSET
IROSC
VDRP
AMP
RMPOUT
VBIAS
VOSNS-
VDAC
VSETPT
RVSETPT
EAOUT
FB
VDRP
IIN
RVFB
RDRP
BIASIN
RAMPIN+
RRAMP1
RAMPIN-
RRAMP2
EAIN
PWMRMP
RPWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
RESET
COMPARATOR DOMINANT
-
R
+
RAMP
SLOPE
ADJUST
SHARE
ADJUST
ERROR
AMP
10K
ENABLE
RAMP
DISCHARGE
CLAMP
+
20mV
-
O% DUTY
CYCLE
COMPARATOR
X
0.91
CURRENT
SENSE
AMP
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
BIASIN
RRAMP1
RAMPIN+
RAMPIN-
RRAMP2
EAIN
PWMRMP
RPWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
RESET
COMPARATOR DOMINANT
-
R
+
RAMP
SLOPE
ADJUST
SHARE
ADJUST
ERROR
AMP
10K
ENABLE
RAMP
DISCHARGE
CLAMP
+
20mV
-
O% DUTY
CYCLE
COMPARATOR
X
0.91
CURRENT
SENSE
AMP
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
VIN
VOSNS+
VOUT
COUT
GND
VOSNS-
Figure 3 – IR3084 PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 4.8V and 0.9V. This signal is used to program both the switching frequency and phase timing of
the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the
VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the
oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the
PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors.
Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be
used for synchronization by swapping the RAMP + and – pins.
Page 8 of 45
07/20/2005
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