M37640E8FP 查看數據表（PDF） - Mitsumi

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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MSB

7

TXM7

TXM6 TXM5

TXM4 TXM3

TXM2

TXM1

TXM0

LSB

0

Address: 002716

Access: R/W

Reset: 0016

TXM0

TXM2,1

TXM3

TXM5,4

TXM6

TXM7

Timer X Data Write Control Bit (bit 0)

0 : Write data in latch and timer

1 : Write data in latch only

Timer X Frequency Division Ratio Bits (bits 2,1)

Bit 2

Bit 1

0

0 : . divided by 8

0

1 : . divided by 16

1

0 : . divided by 32

1

1: .divided by 64

Timer X Internal Clock Select (bit 3)

0 : ./n

1 : SCSGCLK (from chip special count source generation)

Timer X Mode Bits (bits 5,4)

Bit 5

Bit 4

0

0 : Timer Mode

0

1 : Pulse output mode

1

0 : Event counter mode

1

1: Pulse width measurement mode

CNTR0 Polarity Select Bit (bit 6)

0 : For event counter mode, clocked by rising edge

For pulse output mode, start from high level output

For CNTR0 inter rupt request, falling edge active

For pulse width measurement mode, measure high period

1 : For event counter mode, clocked on falling edge

For pulse output mode, start from low level output

For CNTR0 interrupt request, rising edge active

For pulse with measurement mode, measure low period

Timer X Stop Bit (bit 7)

0 : Count start

1 : Count stop

Fig. 1.33. Timer X Mode Register (TXM )

1.17.1 Timer X

Timer X is a 16-bit timer that has a 16-bit reload latch,

and can be placed in one of four modes by setting bits

TXM4 and TXM5 (bits 4 and 5 of the Mode Register,

TXM). The bit assignment of the TXM is shown in Fig-

ure 1.33.

1.17.1.1 Read and Write Method

Read and write operations on the high and low-order

bytes of Timer X must be performed in a specific or-

der.

•Write Method

When writing to the timer, the lower order byte is

written first. This data is placed in a temporary reg-

ister that is assigned the same address as Timer

XL. Next, the higher order byte is written. When this

is done, the data is placed in the Timer XH reload

latch and the low-order byte is transferred from its

temporary register to the Timer XL reload latch. At

this point, if the Timer X Data Write Control Bit

(TXM0) (bit 0) is “0”, the value in the Timer X reload

latch is also loaded in Timer X. If TXM0 is “0”, the

data in the Timer X reload latch is loaded in Timer X

after Timer X underflows.

•Read Method

When reading Timer X, the high-order byte is real

first. Reading the high-order byte causes the values

of Timer XH and Timer XL to be placed in temporary

registers assigned the same addresses as Timer

XH and Timer XL. The low-order byte of Timer X is

then read from its temporary register. This operation

assures the correct reading of Timer X while it is

counting.

1.17.1.2 Count Stop Control

If the Timer X Count Stop Bit (TXM7) (bit 7 of the TXM)

is set to a “1”, Timer X stops counting in all four modes.

•Timer Mode

Count Source: F/n (where n is 8, 16, 32, or 64) or

SCSGCLK

In this mode, each time the timer underflows, the cor-

responding timer interrupt request bit is set to a “1”,

the contents of the timer latch are loaded into the

timer, and the count down sequence begins again.

31

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