MC145192DT 查看數據表（PDF） - Motorola => Freescale

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MC145192DT

Low-Voltage 1.1 GHz PLL Frequency Synthesizer

Motorola => Freescale 

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: current–

sourcing pulses from a floating state

Frequency of fV < fR or Phase of fV Lagging fR: current–

sinking pulses from a floating state

Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter

This output can be enabled, disabled, and inverted via the

C register. If desired, PDout can be forced to the floating state

by utilization of the disable feature in the C register (bit C6).

This is a patented feature. Similarly, PDout is forced to the

floating state when the device is put into standby (STBY bit

C4 = high).

The PDout circuit is powered by VPD. The phase detector

gain is controllable by bits C3, C2, and C1: gain (in amps per

radian) = PDout current divided by 2π.

φR and φV (Pins 3 and 4)

Double–Ended Phase/Frequency Detector Outputs.

These outputs can be combined externally to generate a

loop error signal. Through use of a Motorola patented tech-

nique, the detector’s dead zone has been eliminated. There-

fore, the phase/frequency detector is characterized by a

linear transfer function. The operation of the phase/fre-

quency detector is described below and is shown in Fig-

ure 19.

POL bit (C7) in the C register = low (see Figure 15)

Frequency of fV > fR or Phase of fV Leading fR: φV = nega-

tive pulses, φR = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φV = essen-

tially high, φR = negative pulses

Frequency and Phase of fV = fR: φV and φR remain essen-

tially high, except for a small minimum time period when

both pulse low in phase

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: φR = nega-

tive pulses, φV = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φR = essen-

tially high, φV = negative pulses

Frequency and Phase of fV = fR: φV and φR remain essen-

tially high, except for a small minimum time period when

both pulse low in phase

These outputs can be enabled, disabled, and inter-

changed via C register bits C6 or C4. This is a patented fea-

ture. Note that when disabled or in standby, φR and φV are

forced to their rest condition (high state).

The φR and φV output signal swing is approximately from

GND to VPD.

LD (Pin 2)

Lock Detector Output. This output is essentially at a high

level with narrow low–going pulses when the loop is locked

(fR and fV of the same phase and frequency). The output

pulses low when fV and fR are out of phase or different fre-

quencies. LD is the logical ANDing of φR and φV. See Fig-

ure 19.

This output can be enabled and disabled via the C register.

This is a patented feature. Upon power up, on–chip initializa-

tion circuitry disables LD to a static low logic level to prevent

a false lock signal. If unused, LD should be disabled and left

open.

The LD output signal swing is approximately from GND to

VDD.

Rx (Pin 8)

External Resistor. A resistor tied between this pin and

GND, in conjunction with bits in the C register, determines

the amount of current that the PDout pin sinks and sources.

When bits C2 and C3 are both set high, the maximum current

is obtained at PDout; see Figure 15 for other values of cur-

rent. To achieve a maximum current of 2 mA, the resistor

should be about 22 kΩ when VPD is 5 V.

When the φR and φV outputs are used, the Rx pin may be

floated.

TEST POINT PINS

Test 1 (Pin 9)

Modulus Control Signal. This pin may be used in conjunc-

tion with the Test 2 pin for access to the on–board 64/65

prescaler. When Test 1 is low, the prescaler divides by 65.

When high, the prescaler divides by 64.

CAUTION

This pin is an unbuffered output and must be

floated in an actual application. This pin may be

attached to an isolated pad with no trace.

Test 2 (Pin 13)

Prescaler Output. This pin may be used to access to the

on–board 64/65 prescaler output.

CAUTION

This pin is an unbuffered output and must be

floated in an actual application. This pin may be

attached to an isolated pad with no trace.

POWER SUPPLY PINS

VDD (Pin 14)

Positive Supply Potential. This pin supplies power to the

main CMOS digital portion of the device. The voltage range

is + 2.7 to + 5.0 V with respect to the GND pin.

For optimum performance, VDD should be bypassed to

GND using a low–inductance capacitor mounted very close

to these pins. Lead lengths on the capacitor should be

minimized.

VCC (Pin 12)

Positive Supply Potential. This pin supplies power to the

RF amp and 64/65 prescaler. The voltage range is + 2.7 to

+ 5.0 V with respect to the GND pin. In the standby mode, the

VCC pin still draws a few milliamps from the power supply.

This current drain can be eliminated with the use of transistor

Q1 as shown in Figure 23.

For optimum performance, VCC should be bypassed to

GND using a low–inductance capacitor mounted very close

to these pins. Lead lengths on the capacitor should be

minimized.

MC145192

10

MOTOROLA

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