MC145192DT 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

比赛名单

MC145192DT

Low-Voltage 1.1 GHz PLL Frequency Synthesizer

Motorola => Freescale 

PIN DESCRIPTIONS

DIGITAL INTERFACE PINS

Data In (Pin 19)

Serial Data Input. The bit stream begins with the MSB and

is shifted in on the low–to–high transition of Clock. The bit

pattern is 1 byte (8 bits) long to access the C or configuration

register, 2 bytes (16 bits) to access the first buffer of the R

register, or 3 bytes (24 bits) to access the A register (see

Table 1). The values in the C, R, and A registers do not

change during shifting because the transfer of data to the

registers is controlled by Enable.

CAUTION

The value programmed for the N–counter must

be greater than or equal to the value of the A–

counter.

The 13 LSBs of the R register are double–buffered. As in-

dicated above, data is latched into the first buffer on a 16–bit

transfer. (The 3 MSBs are not double–buffered and have an

immediate effect after a 16–bit transfer.) The second buffer of

the R register contains the 13 bits for the R counter. This sec-

ond buffer is loaded with the contents of the first buffer when

the A register is loaded (a 24–bit transfer). This allows pres-

enting new values to the R, A, and N counters simulta-

neously. If this is not required, then the 16–bit transfer may

be followed by pulsing Enable low with no signal on the Clock

pin. This is an alternate method of transferring data to the

second buffer of the R register. See Figure 17.

The bit stream needs neither address nor steering bits due

to the innovative BitGrabber registers. Therefore, all bits in

the stream are available to be data for the three registers.

Random access of any register is provided. That is, the reg-

isters may be accessed in any sequence. Data is retained in

the registers over a supply range of 2.7 to 5.0 V. The formats

are shown in Figures 15, 16, and 17.

Data In typically switches near 50% of VDD to maximize

noise immunity. This input can be directly interfaced to

CMOS devices with outputs guaranteed to switch near rail–

to–rail. When interfacing to NMOS or TTL devices, either a

level shifter (MC74HC14A, MC14504B) or pull–up resistor of

1 kΩ to 10 kΩ must be used. Parameters to consider when

sizing the resistor are worst–case IOL of the driving device,

maximum tolerable power consumption, and maximum data

rate.

Table 1. Register Access

(MSBs are shifted in first, C0, R0, and A0 are the LSBs)

Number

of Clocks

Accessed

Register

Bit

Nomenclature

8

16

24

Other Values ≤ 32

Values > 32

C Register

R Register

A Register

Not Allowed

See Figures 24

to 27

C7, C6, C5, . . ., C0

R15, R14, R13, . . ., R0

A23, A22, A21, . . ., A0

Clock (Pin 18)

Serial Data Clock Input. Low–to–high transitions on Clock

shift bits available at the Data pin, while high–to–low transi-

tions shift bits from Output A (when configured as Data Out,

see Pin 16). The 24–1/2–stage shift register is static,

allowing clock rates down to dc in a continuous or intermit-

tent mode.

Eight clock cycles are required to access the C register.

Sixteen clock cycles are needed for the first buffer of the R

register. Twenty–four cycles are used to access the A regis-

ter. See Table 1 and Figures 15, 16, and 17. The number of

clocks required for cascaded devices is shown in Figures 25

through 27.

Clock typically switches near 50% of VDD and has a

Schmitt–triggered input buffer. Slow Clock rise and fall times

are allowed. See the last paragraph of Data In for more

information.

NOTE

To guarantee proper operation of the power–on

reset (POR) circuit, the Clock pin must be held at

GND (with Enable being a don’t care) or Enable

must be held at the potential of the V+ pin (with

Clock being a don’t care) during power–up. As an

alternative, the bit sequence of Figure 18 may be

used.

Enable (Pin 17)

Active–Low Enable Input. This pin is used to activate the

serial interface to allow the transfer of data to/from the de-

vice. When Enable is in an inactive high state, shifting is in-

hibited and the port is held in the initialized state. To transfer

data to the device, Enable (which must start inactive high) is

taken low, a serial transfer is made via Data In and Clock,

and Enable is taken back high. The low–to–high transition on

Enable transfers data to the C or A registers and first buffer

of the R register, depending on the data stream length per

Table 1.

NOTE

Transitions on Enable must not be attempted

while Clock is high. This will put the device out of

synchronization with the microcontroller. Resyn-

chronization occurs when Enable is high and

Clock is low.

This input is also Schmitt–triggered and switches near

50% of VDD, thereby minimizing the chance of loading erro-

neous data into the registers. See the last paragraph of Data

In for more information.

For POR information, see the note for the Clock pin.

Output A (Pin 16)

Configurable Digital Output. Output A is selectable as fR,

fV, Data Out, or Port. Bits A22 and A23 in the A register con-

trol the selection; see Figure 16.

If A23 = A22 = high, Output A is configured as fR. This sig-

nal is the buffered output of the 13–stage R counter. The fR

signal appears as normally low and pulses high. The fR sig-

nal can be used to verify the divide ratio of the R counter.

This ratio extends from 5 to 8191 and is determined by the

binary value loaded into bits R0 through R12 in the R regis-

ter. Also, direct access to the phase detectors via the REFin

pin is allowed by choosing a divide value of one. See Fig-

ure 17. The maximum frequency at which the phase detec-

tors operate is 1 MHz. Therefore, the frequency of fR should

not exceed 1 MHz.

If A23 = high and A22 = low, Output A is configured as fV.

This signal is the buffered output of the 12–stage N counter.

MC145192

8

MOTOROLA

Share Link: