AD7701 查看數據表（PDF） - Analog Devices
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AD7701 Datasheet PDF : 20 Pages
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AD7701
The output settling of the AD7701 in response to a step input
change is shown in Figure 12. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
± 0.0007% (± 0.5 LSB) is 125 ms with a 4.096 MHz master
clock frequency.
The input sampling frequency, output data rate, filter character-
istics, and calibration time are all directly related to the master
clock frequency, fCLKIN, by the ratios given in the specification
table. Therefore, the first step in system design with the AD7701 is
to select a master clock frequency suitable for the bandwidth
and output data rate required by the application.
100
80
60
40
20
0
0
40
80
120
160
TIME – ms
Figure 12. AD7701 Step Response
USING THE AD7701
SYSTEM DESIGN CONSIDERATIONS
The AD7701 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the
signal continuously, like a tracking ADC, there is no need for a
start convert command. The 16-bit output register is updated at
a 4 kHz rate, and the output can be read at any time, either
synchronously or asynchronously.
CLOCKING
The AD7701 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
CLKIN pin (CLKOUT not used). Alternatively, a crystal of
the correct frequency can be connected between CLKIN and
CLKOUT, when the clock circuit will function as a crystal
controlled oscillator.
ANALOG INPUT RANGES
The AD7701 performs conversion relative to an externally
supplied reference voltage that allows easy interfacing to
ratiometric systems. In addition, either unipolar or bipolar input
voltage ranges may be selected using the BP/UP input. With
BP/UP tied low, the input range is unipolar and the span is 0 to
+VREF. With BP/UP tied high, the input range is bipolar and the
span is ± VREF. In the Bipolar mode, both positive and negative
full scale are directly determined by VREF. This offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
The digital output coding for the unipolar range is unipolar
binary; for the bipolar range it is offset binary. Bit weights for
the Unipolar and Bipolar modes are shown in Table I. The
input voltages and output codes for unipolar and bipolar ranges,
using the recommended +2.5 V reference, are shown in
Table II.
Table I. Bit Weight Table (2.5 V Reference Voltage)
Unipolar Mode
µV LSBs % FS ppm FS
10 0.26
19 0.5
38 1.00
76 2.00
153 4.00
0.0004 4
0.0008 8
0.0015 15
0.0031 31
0.0061 61
Bipolar Mode
LSBs % FS ppm FS
0.13 0.0002 2
0.26 0.0004 4
0.5 0.0008 8
1.00 0.0015 15
2.00 0.0031 31
Unipolar Mode
Input Relative to
FS and AGND
Input (V)
Table II. Output Coding
Bipolar Mode
Input Relative to
FS and AGND Input (V)
+VREF – 1.5 LSB
+VREF – 2.5 LSB
+VREF – 3.5 LSB
+2.499943
+2.499905
+2.499867
+VREF – 1.5 LSB
+VREF – 2.5 LSB
+VREF – 3.5 LSB
+2.499886
+2.499810
+2.499733
Output Data
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
+VREF/2 + 0.5 LSB
+VREF/2 – 0.5 LSB
+VREF/2 – 1.5 LSB
+1.250019
+1.249981
+1.249943
AGND + 0.5 LSB +0.000038
AGND – 0.5 LSB –0.000038
AGND – 1.5 LSB –0.000114
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
AGND + 2.5 LSB
AGND + 1.5 LSB
AGND + 0.5 LSB
+0.000095
+0.000057
+0.000019
–VREF + 2.5 LSB
–VREF + 1.5 LSB
–VREF + 0.5 LSB
NOTES
1. VREF = 2.5 V
2. AGND = 0 V
3. Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V
4. Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V
5. Inputs are voltages at code transitions.
–10–
–2.499810
–2.499886
–2.499962
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
REV. E
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