MM74HC595 查看數據表（PDF） - Fairchild Semiconductor

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比赛名单

MM74HC595

8-Bit Shift Register with Output Latches

Fairchild Semiconductor 

Physical Dimensions

10.00

9.80

8.89

16

A

9

B

1.75

6.00

4.00

3.80

5.6

PIN ONE

INDICATOR

1

1.27

(0.30)

8

0.51

0.35

0.25 M C B A

1.27

0.65

LAND PATTERN RECOMMENDATION

1.75 MAX

1.50

1.25

0.25

0.10

C

0.10 C

SEE DETAIL A

0.25

0.19

(R0.10)

(R0.10)

8°

0°

0.90

0.50

(1.04)

0.50

0.25

X 45°

GAGE PLANE

0.36

SEATING PLANE

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AC, ISSUE C.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD

FLASH AND TIE BAR PROTRUSIONS

D) CONFORMS TO ASME Y14.5M-1994

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM

F) DRAWING FILE NAME: M16AREV12.

DETAIL A

SCALE: 2:1

Figure 4. 16-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Inch Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

© 1983 Fairchild Semiconductor Corporation

MM74HC595 • Rev. 1.0.2

10

www.fairchildsemi.com

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