MM74HC595 查看數據表（PDF） - Fairchild Semiconductor
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MM74HC595 Datasheet PDF : 14 Pages
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Pin Configuration
Figure 2. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
QB
QC
QD
QE
QF
QG
QH
GND
Q’H
SCLR
SCK
RCK
G
SER
QA
VCC
Description
Output Bit B
Output Bit C
Output Bit D
Output Bit E
Output Bit F
Output Bit G
Output Bit H
Ground
Serial Data Output
Shift Register Clear
Shift Register Clock Input
Storage Register Clock Input
Output Enable
Serial Data Input
Output Bit A
Supply Voltage
Truth Table
RCK
X
X
SCK
X
X
SCLR
X
L
X
↑
H
↑
X
H
L = Logic Level LOW
H = Logic Level HIGH
X = Don’t Care
↑ = Transition from LOW to HIGH level
G
Function
H
QA through QH = 3-state
L
Shift register clocked; Q’H = 0
L
Shift register clocked; QN = Qn-1, Q0 = SER
L
Contents of shift; register transferred to output latches
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
3
www.fairchildsemi.com
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