NJU3504FA1 查看數據表（PDF） - Japan Radio Corporation

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NJU3504FA1

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3504

• TIMER2 CONTROL REGISTER {PHY5 ; (Y'=5, Peripheral register table 0)}

[Writing to the Timer2 Control Register]

(MSB) 3

2

1

0 (LSB)

PHY5

Start control

/ 1:Start

Operation mode / 0:Single mode, 1:Repeat mode

Count clock type / 0:Internal clock, 1:External clock

Count clock mask / 0:Mask, 1: Non-mask

When the bit3(b3) of this Timer2 Control

Register is set to "0", the internal or external clock

is stopped to supply to the Timer2.

EX.)An example of the start procedure for the repeat mode, the external clock operation and releasing the

count clock mask.

:

:

SRPC

;

LDI

Y,5

;PHY5(Timer2 Control Register) is pointed.

LDI

A,%1110 ;"1110"(BIN) is stored to accumulator Repeat mode, External

TAP

;Data is transferred from accumulator to PHY5

clock operation.

LDI

A,%1111 ;"1111"(BIN) is stored to accumulator

TAP

;Data is transferred from accumulator to PHY5

The count is started.

:

:

Remarks) In the Timer2 operation, when the count clock mask bit(b3) of the Timer2 Control Register is set to "0",

the Timer2 is stopped to count and it holds the latest data of the 8-bit counter2. When the b3 is set to

"1", the Timer2 starts to count from the hold data of the 8-bit counter2.

[Reading from the Timer2 Control Register]

(MSB) 3

2

1

0 (LSB)

PHY5

Overflow flag

/ 1: Overflow

Operation mode / 0:Single mode, 1:Repeat mode

Count clock type / 0:Internal clock, 1:External clock

Count clock mask / 0:Mask, 1: Non-mask

EX.)An example of the Timer2 starting information as the Single mode, the internal clock operation and the

released clock mask.(The data of Timer2 Control Register is "1001"(BIN).)

:

:

SRPC

LDI

Y,5

TPA

:

:

;

;PHY5(Timer2 Control Register) is pointed

;Data is transferred "1001"(BIN) of PHY5 to accumulator

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