NJU3504
s A/D CONVERTER
The A/D converter operates with the following specification.
• A/D Conversion
: Successive Approximation method
• Minimum conversion Time
: 40µsec (VDD=5V, VREF=5V, fADCK=225kHz)
• Resolution
: 8 bit (256 step)
• Absolute Accuracy
: ±2 LSB (VDD=5V, VREF=5V)
• Reference Voltage
• Analog Input Voltage
• Channel
: 2.4V−AVDD
: AVSS −VREF
: Multiplexed 4-channel Input
The A/D converter block diagram and the timing chart are shown below.
The lower 2 bits of the A/D control register are the switches to select an analog input channel from four
multiplexed inputs(AIN0 to AIN3). The analog input signal to the analog input port selected by the A/D control
register is converted to the digital data, and then the digital data is stored into the A/D output register(PHY8).
The A/D control clock can selected either the external clock or the internal by the mask option. In the
external clock operation, the input clock from the “ADCK” terminal operates as the A/D control clock. In the
internal clock operation, the clock divided in the internal Prescaler operates as the A/D control clock. The
frequency of the clock from the internal Prescaler can be selected by the mask option from follows which are
dividing numbers based on the inverse of one instruction execution time(1/fOSC X 6).
1/2, 1/4, 1/8, 1/16, 1/32,1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048, 1/4096
[A/D CONVERTER BLOCK DIAGRAM]
DB
PRESCALER
A/D CONTROL 4
REGISTER
START
CONTROL CIRCUIT
4
4
EOC
COMPARATOR
Upper side
4bit data
YLSB=“1”
Lower side
4bit data
YLSB=“0”
AIN3
AIN2
A/D OUTPUT REGISTER
AIN1
AIN0
SWITCH TREE
LADDER RESISTOR
AVSS
VREF
ADCK
Remarks) The A/D control clock can be selected either the external clock from the ADCK terminal or the internal
clock from the Prescaler by the mask option. The Prescaler supplies clocks to Timer/Counter, Serial
Input Output, and A/D converter.
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