PDI1394L40 查看數據表（PDF） - Philips Electronics
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PDI1394L40 Datasheet PDF : 80 Pages
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Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
16.0 TIMING DIAGRAMS
16.1 AV Interface Operation
AVCLK
AV D[7:0]
MESSAGE
AVSYNC
INVALID DATA
MESSAGE
INVALID DATA
AVVALID
AVERR[0]
AVERR[1]
ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR
ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR
Figure 35. AV Parallel Interface Operation Diagram
16.2 AV Interface Critical Timings
AVCLK
ÉÉÉ AV D [7:0], AVVALID,
ÉÉÉ AVSYNC, AVENDPCK
SY, READY
AV D [7:0], AVERR[1:0],
AVSYNC, AVVALID
ÉÉÉÉÉÉ VALID
tWHIGH
tSU
tIH
tOD
tPERIOD
tWLOW
VALID
Figure 36. AV Interface Timing Diagram
MESSAGE
SV00240
SV01870
AVxFSYNC
tPWFS
SV00890
NOTE:
1. Timing shown is for AVxFSYNC used as an output only. When AVxFSYNC is used as an input, only the rising edge of the signal is
considered as long as the input pulse width exceeds 40 nS.
Figure 37. AVxFSYNC Timing Diagram
2000 Dec 15
70
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