PDI1394L40 查看數據表（PDF） - Philips Electronics
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PDI1394L40 Datasheet PDF : 80 Pages
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Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
16.4 Host Interface Critical Timings
READ
tAS
tAS
HIF A[7:0]
VALID
tCL
HIF CS_N
tRP
HIF RD_N
HIF D[7:0]
tAS ÉÉÉÉÉÉÉÉÉÉÉÉtAÉÉÉCC ÉÉÉÉÉÉÉÉÉÉÉÉ
A8
WAIT
tWAIT
tPWWAIT
tAH
tAH
tCH
VALID
tDZ
WRITE
HIF WR_N
tWRP
HIF D[7:0]
tDS
A8
VALID
WAIT
tWAIT
NOTE:
1. Wait line asserts only during Read and Write cycles in which A8 is asserted.
Figure 40. Host Interface Timing Waveforms
16.5 CYCLEIN/CYCLEOUT Timings
CYCLEIN
50%
50%
50%
tCWH
tCWL
tCP
Figure 41. CYCLEIN Waveform
2000 Dec 15
72
tDH
SV00696
SV01776
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