PLL103-07 查看數據表（PDF） - PhaseLink Corporation
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PLL103-07 Datasheet PDF : 7 Pages
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Preliminary PLL103-07
2 DIMM DDR Fanout Buffer
PIN DESCRIPTIONS
Name
FBOUT
BUF_IN
DDRT[0:5]
DDRC[0:5]
VDD2.5
GND
Number
1
10
3,7,12,19,
23,27
4,8,13,18,
22,26
5,9,14,
17,21,25
6,11,20,24
Type
Description
O Feedback clock for chipset.
I Reference input from chipset.
O “True” clocks of differential pair outputs.
O “Complementary” clocks of differential pair outputs.
P 2.5V power supply.
P Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 2
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