PLL103-07 查看數據表（PDF） - PhaseLink Corporation

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PLL103-07

2 DIMM DDR Fanout Buffer

PhaseLink Corporation 

Preliminary PLL103-07

2 DIMM DDR Fanout Buffer

2. BYTE 7: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

-

1

Reserved

Bit 6

-

1

Reserved

Bit 5

-

1

Reserved

Bit 4

12, 13

Bit 3

-

1

DDRT2, DDRC2

1

Reserved

Bit 2

7, 8

1

DDRT1, DDRC1

Bit 1

-

1

Reserved

Bit 0

3, 4

1

DDRT0, DDRC0

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/03/01 Page 4

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