UPD98401AGD-MML 查看數據表（PDF） - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

1. PIN FUNCTION

The µPD98401A is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are VDD

and GND pins.

1.1 PHY Device Interface Pin

PHY device interfaces include a UTOPIA interface through which the µPD98401A transfers ATM cells with a PHY

device, and a PHY control interface by which the µPD98401A controls the PHY device.

(1) UTOPIA interface

Pin Name

Pin No.

I/O

I/O Level

Function

(1/2)

Rx7-Rx4

74 - 77

I

Rx3-Rx0

80 - 83

TTL

Receive Data Bus.

Rx7 through Rx0 constitute an 8-bit input bus which inputs data

received from a network in byte format from a PHY device. The

µPD98401A loads data in at the rising edge of RCLK.

RSOC

86

I

TTL

Receive Start Cell.

The RSOC signal is input in synchronization with the first byte of the

cell data from a PHY device. This signal remains high while the first

byte of the header is input to Rx7 through Rx0.

RENBL_B

85

O

CMOS

Receive Enable.

The RENBL_B signal indicates to a PHY device that the µPD98401A

is ready to receive data in the next clock cycle. This signal goes high

during and after reset.

EMPTY_B/

87

I

TTL

PHY Output Buffer Empty/Rx Cell Available.

RxCLAV

This signal notifies the µPD98401A that there is no cell data to be

transferred in the receive FIFO and that no receive data can be

supplied to the PHY device. When the UTOPIA interface is in the

octet-level handshake mode, this signal serves as EMPTY_B,

indicating that the data on Rx7 through Rx0 are invalid in the current

clock cycle. In the cell-level handshake mode, it serves as RxCLAV,

indicating that there is no cell to be supplied next after the transfer of

the current cell is completed.

RCLK

84

O

CMOS

Receive Clock.

This is a synchronization clock used to transfer cell data with the PHY

cell device at the recieve side. The system clock input to the CLK pin

is output from this pin as is, immediately after reset.

Tx7-Tx0

95 - 102

O

CMOS

Transmit Data Bus.

Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit

data in byte format to a PHY device. The µPD98401A outputs data at

the rising edge of TCLK.

TSOC

89

O

CMOS

Transmit Start of Cell.

The TSOC signal is output in synchronization with the first byte of

transmit cell data.

Data Sheet S12100EJ3V0DS00

7

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