UPD98401AGD-MML 查看數據表（PDF） - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

1.2 Bus Interface Pins

The bus interface is a general-purpose bus interface compatible with most generally used I/O buses (such as PCI,

S bus, GIO, and AP bus).

(1/3)

Pin Name

Pin No.

I/O

I/O Level

Function

AD31-AD27

AD26-AD22

AD21-AD17

AD16-AD13

AD12

AD11-AD7

AD6-AD0

3-7

9 - 13

16 - 20

22 - 25

28

35 - 39

42 - 48

I/O

3-state

TTL in

CMOS out

Address/Data.

AD31 through AD0 constitute a 32-bit address/data bus. These pins

are I/O pins multiplexing an address bus and a data bus. At the first

clock of input/output, AD31 through AD0 transfer an address. They

transfer data at the second clock and onward. The AD bus goes into

a high-impedance state when the µPD98401A does not access the

bus.

PAR3

PAR2

PAR1

PAR0

49

I/O

TTL in

Bus Parity.

50

3-state CMOS out PAR pins indicate the parity of AD31 through AD0. A parity check

54

mode is set by GMR. Enabling or disabling parity, odd or even parity,

55

and word or byte parity can be specified. If byte parity is specified,

PAR3 indicates the parity of AD31 through AD24, and PAR0 indicates

the parity of AD7 through AD0. If word parity is specified, PAR3

serves as an input/output pin. It serves as an output pin when an

address is output and when data is written, and as an input pin when

data is read.

When the µPD98401A does not access the bus, PAR3 through PAR0

go into a high-impedance state. Pull up these pins when they are not

used.

OE_B

56

I

TTL

Output Enable.

When this pin is low, the µPD98401A uses AD31 through AD0 and

PAR3 through PAR0 as 3-state I/O pins. These pins go into a high-

impedance state while a high level is being input to OE_B. This pin is

an option pin. Fix this pin to low level in a system where it is not

necessary to forcibly set the bus of the µPD98401A in a high-

impedance state by controlling this pin.

SIZE2

SIZE1

SIZE0

57

O

CMOS

Burst Size.

60

SIZE2 through SIZE0 indicate the size of the current DMA transfer.

61

These pins are used to interface a bus (such as S bus) requiring clear

burst size.

SIZE2

0

0

0

0

1

1

1

1

SIZE1

0

0

1

1

0

0

1

1

SIZE0

0

1

0

1

0

1

0

1

Function

1-word transfer

2-word burst

4-word burst

8-word burst

16-word burst

12-word burst

Undefined

Reception side byte alignment

Data Sheet S12100EJ3V0DS00

9

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