LA7945N 查看數據表（PDF） - SANYO -> Panasonic

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LA7945N

Closed Caption Signal (US specifications) Extraction IC

SANYO -> Panasonic 

LA7945N

• Pin 14 (AFC2) : Used for phase adjustment of the internal VCO CLOCK and CLK-RUN-IN

A signal is output from pin 14 only during the 21H CLK-RUN-IN period,

and the phase is adjusted by controlling the fixed current determined by the

15kΩ resistor on pin 12 only during that period.

• Pin 15 (CLOCK PHASE) : CLOCK-RUN-IN phase compensation pin.

Only the CLK-RUN-IN signal during the vertical retrace period is extracted

and passed to the multiplier described above. The phase of the clock output

from pin 5 can be adjusted by the value of the capacitor (C1) connected to

this pin.

Figure 6 : Pin 14 (AFC2) and Pin 15 (CLOCK PHASE) Peripheral Circuit

• Pin 17 (VIDEO IN) : The video input pin. (sync-white 1 Vp-p)

Pin 17 is designed to clamp the pedestal level at 1/2 VCC. Since C1 also

functions as the clamping capacitor, it should be driven with a low imped-

ance (less than 500Ω). The low field performance can be improved by add-

ing an LPF such as R1 and C2. If this LPF is used, R1 must be a low resis-

tance that can meet the conditions described above.

Figure 7 : Pin 17 (VIDEO IN) Peripheral Circuit

No.4616–7/9

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