ADG728(2000) 查看數據表（PDF） - Analog Devices

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ADG728
(Rev.:2000)

CMOS, Low-Voltage, 2-Wire Serially-Controlled, Matrix Switches

Analog Devices 

ADG728/ADG729

WRITE OPERATION

When writing to the ADG728/ADG729, the user must begin

with an address byte and R/W bit, after which the switch will

acknowledge that it is prepared to receive data by pulling SDA

low. This address byte is followed by the 8-bit word. The write

operations for each matrix switch are shown in the figures below.

SCL

SDA

1

START

COND

BY

MASTER

0

0

1

1

ADDRESS BYTE

A1 A0 R/W

S8 S7 S6 S5 S4 S3 S2 S1

ACK

BY

ADG728

DATA BYTE

ACK STOP

BY COND

ADG728 BY

MASTER

Figure 16. ADG728 Write Sequence

SCL

SDA

1

START

COND

BY

MASTER

0

0

0

1

ADDRESS BYTE

A1 A0 R/W

S8 S7 S6 S5 S4 S3 S2 S1

ACK

BY

ADG729

DATA BYTE

ACK STOP

BY COND

ADG729 BY

MASTER

Figure 17. ADG729 Write Sequence

READ OPERATION

When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the ma-

trix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that

consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19.

SCL

SDA

1

START

COND

BY

MASTER

0

0

1

1

ADDRESS BYTE

A1 A0 R/W

S8 S7 S6 S5 S4 S3 S2 S1

ACK

BY

ADG728

DATA BYTE

NO ACK STOP

BY COND

MASTER BY

MASTER

Figure 18. ADG728 Readback Sequence

SCL

SDA

1

START

COND

BY

MASTER

0

0

0

1

ADDRESS BYTE

A1 A0 R/W

S8 S7 S6 S5 S4 S3 S2 S1

ACK

BY

ADG729

DATA BYTE

NO ACK STOP

BY COND

MASTER BY

MASTER

Figure 19. ADG729 Readback Sequence

–10–

REV. A

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