ST70136G 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

比赛名单

ST70136G

CPE ADSL ANALOG FRONT END

STMicroelectronics 

ST70136

2.11.2 - TOP

This pin is the differential non-inverting tone

detector input.

2.11.3 - ACTD

This pin is active when tone 40 or 72 has been

detected in sleeping mode (see control register)

2.12 - CRYSTAL

These pins must be tied to an external crystal

(F = 35.328MHz).

2.12.1 - XTALI

This pin is the crystal oscillator input.

2.12.2 - XTALO

This pin is the crystal oscillator output.

2.13 - VCXO

2.13.1 - IVCO

This pin is the current reference for the VCO DAC

2.13.2 - VCOCAP

This pin is used to introduce time constant. The

tuning is done by connecting an external capacitor

2.13.3 - VCXOUT

This pin is the output control current generated by

a 8 bit DAC.

2.14 - Control Serial Interface

Access to the control register can be done only in

stable state fonctionality:

SUSPEND = "0".

2.14.1 - CTRLIN

This pin is used to program the internal registers.

The data burst is composed of 16 bits sampled at

CLKM when CLKWD = 1. The first bit is used as

start bit (’0’), the three LSBs being used to identify

the data contained in the twelve remaining bits.

The start bit b15 (b5 = 0) is transmitted first fol-

lowed by bits b[14:0]. At least 1 stop bit "1" need

to be provided to validate the data.

2.14.2 - CTRLOUT

This pin is the control register output. The burst

data on this pin is the value of the register

addressed by CTRLIN.

2.14.3 - CLKWD

This pin is the word clock used to sample the con-

trol information and equal to CLKM / 4.

2.14.4 - R/NW

This pin is used for the read and write operation

for the control interface and sampled at the same

time than bit b15 of CTRLIN.

2.14.5 - Digital Interface

The interface is a nibble serial interface running at

8.832MHz sampling frequency. The data are pre-

sented in 16bits format, and transferred in groups

of 4 bits (nibbles). The LSBs are transferred first.

Data is transmitted on the rising edge of the mas-

ter clock CLKM

2.14.6 - CLKM

This pin is the master clock equal to 35.328MHz

and is the sampling clock of the input / output

data.

2.14.7 - TX0, TX1, TX2, TX3

These pins are the digital transmit data input.

2.14.8 - RX0, RX1, RX2, RX3

These pins are the digital receive data output.

2.15 - Test

This pin is dedicated to put the ST70136 in test

mode.

6/24

Share Link: