W742C814 查看數據表（PDF） - Winbond

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W742C814

4-BIT MICROCONTROLLER

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W742C814

6.8 Dividers

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.

When the main oscillator starts action, the Divider0 is incremented by each clock (FOSC). When an

overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable

flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been

set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by

executing CLR DIVR0 instruction.

If the Fslow-oscillator starts action, the Divider1 is incremented by each clock. When an overflow

occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has

been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set

(HEF.4 = 1), the hold state is terminated. And the last 4-stage of the Divider1 can be reset by

executing CLR DIVR1 instruction. Same as EVF.0, the EVF.4 is set to 1 periodically. But there are two

period time (125 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0

(default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.

6.9 Dual-clock Operation

In the dual-clock mode, before the STOP instruction is executing, the LCD must be turned off.

the normal operation is performed by generating the system clock from the Fslow-oscillator clock. As

required, the fast operation can be performed by generating the system clock from the Ffast-oscillator

clock. The exchange of the normal operation and the fast operation is performed by setting the bit 0 of

the System clock Control Register (SCR). If the SCR.0 is reset to 0, the clock source of the system

clock generator is Fslow-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock

generator is Ffast-oscillator clock. In the dual-clock mode, the Fosc-oscillator can stop oscillating

when the STOP instruction is executing or the SCR.1 is set to 1.

When the SCR is set or reset, we must care the following cases:

1. XX00B → XX11B: we should not exchange the FOSC from Fslow into Ffast and enable

Ffast simultaneously. We could first the SCR.1 is set to 1 to enable PLL, the 2nd step is

calling a delay subroutine to wait the Ffast-oscillator oscillating stably; then exchange the

FOSC from Fslow into Ffast is the last step. So it should be XX00B→XX10B→delay the Ffast

oscillating stably time→XX11B. The suggestion of the Ffast oscillating stably time is 25

mS(Min.) for PLL stable output 3.6042 MHz.

2. X011B → X000B: we should not exchange Fosc from Ffast into Fslow and disable Ffast

simultaneously. exchange the FOSC from Fs into Fm simultaneously. We could first exchange

the Fosc from Ffast into Fslow, then disable the PLL. So it should be XX11B → XX10B →

XX00B.

We must remember that the XX01B state is inhibitive, because it will induce the system

shutdown.

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