ST16C2450(2003) 查看數據表（PDF） - Exar Corporation
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ST16C2450 Datasheet PDF : 29 Pages
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REV. 4.0.0
ST16C2450
2.97V TO 5.5V DUART
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING
TEMPERATURE
RANGE
DEVICE STATUS
ST16C2450CP40 40-Lead PDIP 0°C to +70°C Active. See the ST16C2450CQ48 for new designs.
ST16C2450CJ44 44-Lead PLCC 0°C to +70°C Active
ST16C2450CQ48 48-Lead TQFP 0°C to +70°C Active
ST16C2450IP40 40-Lead PDIP -40°C to +85°C Active. See the ST16C2450IQ48 for new designs.
ST16C2450IJ44 44-Lead PLCC -40°C to +85°C Active
ST16C2450IQ48 48-Lead TQFP -40°C to +85°C Active
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC 48-TQFP
PIN #
PIN #
DATA BUS INTERFACE
A2
29
26
A1
30
27
A0
31
28
D7
9
3
D6
8
2
D5
7
1
D4
6
48
D3
5
47
D2
4
46
D1
3
45
D0
2
44
IOR#
24
19
IOW#
20
15
CSA#
16
10
CSB#
17
11
INTA
33
30
TYPE
DESCRIPTION
I Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
IO Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
I Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
I UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
I UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
O UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
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