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ST16C2450(2003) 查看數據表(PDF) - Exar Corporation

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产品描述 (功能)
比赛名单
ST16C2450
(Rev.:2003)
Exar
Exar Corporation Exar
ST16C2450 Datasheet PDF : 29 Pages
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áç
REV. 4.0.0
ST16C2450
2.97V TO 5.5V DUART
2.3 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the user to
select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART.
Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do
not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT
CSA#
1
0
1
0
CSB#
1
1
0
0
FUNCTION
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
2.4 Channel A and B Internal Registers
Each UART channel in the 2450 has a standard register set for controlling, monitoring and data loading and
unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratch pad register
(SPR).
2.5 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 2 summarizes the operating behavior for the transmitter and receiver. Also see Figure 12 and Figure 13.
INTA/B Pin
TABLE 2: INTA AND INTB PINS OPERATION FOR TRANSMITTER
TRANSMITTER
RECEIVER
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
2.6 Crystal Oscillator or External Clock Input
The 2450 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. See “Programmable Baud Rate
Generator” on page 8.
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