AD9430BSVZ-170 查看數據表（PDF） - Analog Devices
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AD9430BSVZ-170 Datasheet PDF : 44 Pages
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AD9430
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Parameter
ENCODE AND DS INPUTS
(CLK+, CLK–, DS+, DS–)1
Differential Input Voltage2
Common-Mode Voltage3
Input Resistance
Input Capacitance
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Resistance
Input Capacitance
LOGIC OUTPUTS (CMOS Mode)
Logic 1 Voltage4
Temp
Full
Full
Full
25°C
Full
Full
Full
Full
25°C
25°C
Full
Logic 0 Voltage4
Full
LOGIC OUTPUTS (LVDS Mode)4, 5
VOD Differential Output Voltage Full
VOS Output Offset Voltage
Full
Output Coding
Test
Level
AD9430-170
Min
Typ
Max
IV
0.2
VI
1.375
1.5
1.575
VI
3.2
5.5
6.5
V
4
IV
2.0
IV
0.8
VI
190
VI
10
V
30
V
4
IV
DRVDD
–0.05
IV
0.05
VI
247
454
VI
1.125
1.375
Twos complement or binary
1 ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section.
2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.
4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF.
5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).
AD9430-210
Min
Typ
Max Unit
0.2
1.375
1.5
3.2
5.5
4
V
1.575 V
6.5
kΩ
pF
2.0
30
4
V
0.8
V
190
μA
10
μA
kΩ
pF
DRVDD
–0.05
V
0.05
V
247
454
mV
1.125
1.375 V
Twos complement or binary
Rev. E | Page 7 of 44
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