AD9430BSVZ-170 查看數據表（PDF） - Analog Devices

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AD9430BSVZ-170

12-Bit, 170/210 MSPS 3.3 V A/D Converter

Analog Devices 

TIMING DIAGRAMS

CLK+

CLK–

DS+

DS–

tHDS

INTERLEAVED DATA OUT

PORT A

DA11–DA0

STATIC

tSDS

14 CYCLES

INVALID

tPD

N

N+2

PORT B

DB11–DB0

STATIC

INVALID

INVALID

N+1

PARALLEL DATA OUT

PORT A

DA11–DA0

STATIC

PORT B

DB11–DB0

STATIC

DCO–

DCO+

STATIC

INVALID

INVALID

INVALID

INVALID

N

N+1

tCPD

Figure 2. CMOS Timing Diagram

tV

N+3

N+2

N+3

AD9430

AIN

CLK+

CLK–

DATA OUT

DCO+

DCO–

N–1

N

N+1

tEL

tEH

1/fS

tPD

N–14

N–13

14 CYCLES

N

N+1

tCPD

Figure 3. LVDS Timing Diagram

Rev. E | Page 9 of 44

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