SCA100T 查看數據表（PDF） - Murata Manufacturing
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SCA100T Datasheet PDF : 17 Pages
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SCA100T Series
1.6 SPI Interface Timing Specifications
Parameter
Terminal CSB, SCK
Time from CSB (10%)
to SCK (90%)
Time from SCK (10%)
to CSB (90%)
Terminal SCK
SCK low time
SCK high time
Terminal MOSI, SCK
Time from changing MOSI
(10%, 90%) to SCK (90%).
Data setup time
Time from SCK (90%) to
changing MOSI (10%,90%).
Data hold time
Terminal MISO, CSB
Time from CSB (10%) to stable
MISO (10%, 90%).
Time from CSB (90%) to high
impedance state of
MISO.
Terminal MISO, SCK
Time from SCK (10%) to stable
MISO (10%, 90%).
Terminal CSB
Time between SPI cycles, CSB at
high level (90%)
When using SPI commands
RDAX, RDAY, RWTR: Time
between conversion cycles, CSB
at high level (90%)
Conditions
Load
capacitance at
MISO < 2 nF
Load
capacitance at
MISO < 2 nF
Load
capacitance at
MISO < 15 pF
Load
capacitance at
MISO < 15 pF
Load
capacitance at
MISO < 15 pF
Symbol Min. Typ. Max. Unit
TLS1
120
ns
TLS2
120
ns
TCL
1
s
TCH
1
s
TSET
30
ns
THOL
30
ns
TVAL1
10
TLZ
10
100 ns
100 ns
TVAL2
100 ns
TLH
15
s
TLH 150
s
TLS1
TCH
TCL
TLS2
TLH
CSB
SCK
THOL
TSET
MOSI
MSB in
DATA in
LSB in
TVAL1
TVAL2
TLZ
MISO
MSB out
DATA out
LSB out
Figure 2. Timing diagram for SPI communication
Murata Electronics Oy
www.muratamems.fi
Subject to changes
Doc. nr. 8261800
5/17
Rev.B2
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