T35L6464A 查看數據表（PDF） - Taiwan Memory Technology
零件编号
产品描述 (功能)
比赛名单
T35L6464A Datasheet PDF : 16 Pages
| |||
tm TE
CH
T35L6464A
PIN DESCRIPTIONS (continued)
QFP PINS
104
105
106
41
63
2-12,15-24,
27-37,66-76,
79-88,91-101
45,58,109,122
46,59,110,123
13,25,38,64,
77,89,102,128
1,14,26,39,65,
78,90,103
40,52
SYM. TYPE
DESCRIPTION
ADV Input- Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
ADSP Input- Address Status Processor: This active LOW input, along withCE
Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
ADSC Input- Address Status Controller:This active LOW input causes device to
Synchronous be de- selected or selected along with new external address to be
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
MODE Input- Mode: This input selects the burst sequence. A LOW on this pin
Static selects LINEAR BURST. A NC or HIGH on this pin selects
INTERLEAVED BURST. Do not alter input state while device is
operating.
ZZ
Input Snooze Enable: This active HIGH asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained.
DQ1- Input/ Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-
DQ64 Output DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25- DQ32.
Fifth Byte is DQ33- DQ40. Sixth Byte is DQ41- DQ48. Seventh
Byte is DQ49- DQ56. Eighth Byte is DQ57- DQ64. Input data
must meet setup and hold times around the rising edge of CLK.
VCC Supply Power Supply: 3.3V +10%/-5%.
VSS Ground Ground: GND
VCCQ I/O Supply Isolated Output Buffer Supply: 3.3V +10%/-5%.
VSSQ I/O Ground Output Buffer Ground: GND
NC
-
No Connect: These signals are not internally conntected.
Taiwan Memory Technology, Inc. reserves the right P. 4
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
Share Link: 