74ABT899 查看數據表（PDF） - Fairchild Semiconductor

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74ABT899

9-Bit Latchable Transceiver with Parity Generator/Checker

Fairchild Semiconductor 

Pin Descriptions

Pin Names

Descriptions

A0–A7

B0–B7

APAR, BPAR

A Bus Data Inputs/Data Outputs

B Bus Data Inputs/Data Outputs

A and B Bus Parity Inputs/Outputs

ODD/EVEN ODD/EVEN Parity Select,

Active LOW for EVEN Parity

GBA, GAB

Output Enables for A or B Bus,

Active LOW

SEL

Select Pin for Feed-Through or

Generate Mode, LOW for Generate

Mode

LEA, LEB

Latch Enables for A and B Latches,

HIGH for Transparent Mode

ERRA, ERRB Error Signals for Checking Generated

Parity with Parity In, LOW if Error

Occurs

Functional Description

The ABT899 has three principal modes of operation which

are outlined below. These modes apply to both the A-to-B

and B-to-A directions.

• Bus A (B) communicates to Bus B (A), parity is gener-

ated and passed on to the B (A) Bus as BPAR (APAR). If

LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,

the parity generated from B[0:7] (A[0:7]) can be checked

and monitored by ERRB (ERRA).

• Bus A (B) communicates to Bus B (A) in a feed-through

mode if SEL is HIGH. Parity is still generated and

checked as ERRA and ERRB in the feed-through mode

(can be used as an interrupt to signal a data/parity bit

error to the CPU).

• Independent Latch Enables (LEA and LEB) allow other

permutations of generating/checking (see Function

Table below).

Function Table

Inputs

Operation

GAB GBA SEL LEA LEB

H H X X X Busses A and B are 3-STATE.

H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.

Generated parity checked against BPAR and output as ERRB.

H L L H H Generates parity from B[0:7] based on O/E. Generated parity → APAR. Gener-

ated parity checked against BPAR and output as ERRB. Generated parity also

fed back through the A latch for generate/check as ERRA.

H L L X L Generates parity from B latch data based on O/E. Generated parity → APAR.

Generated parity checked against latched BPAR and output as ERRB.

H L H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked

against BPAR and output as ERRB.

H L H H H BPAR/B[0:7] → APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and output as

ERRB. Generated parity also fed back through the A latch for generate/check as

ERRA.

L H L H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Gener-

ated parity checked against APAR and output as ERRA.

L H L H H Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Gener-

ated parity checked against APAR and output as ERRA. Generated parity also

fed back through the B latch for generate/check as ERRB.

L H L L X Generates parity from A latch data based on O/E. Generated parity → BPAR.

Generated parity checked against latched APAR and output as ERRA.

L H H H L APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA.

L H H H H APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA. Generated parity also fed back through the B latch for generate/check as

ERRB.

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Note 1: O/E = ODD/EVEN

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